1. Field of the Invention
The present invention relates to an automatic cell placement and routing method, in which cells to be arranged in a semiconductor integrated circuit are automatically placed to design a layout pattern of the cells, and a semiconductor integrated circuit in which timing considered cells automatically placed according to the automatic cell placement and routing method in the design of a layout pattern of the timing-considered cells are arranged with a timing-free-cell.
2. Description of Related Art
In cases where a plurality of timing-considered cells connected with each other on a signal path are to be arranged in a semiconductor integrated circuit on condition that an input timing of a signal input to each timing-considered cell is considered, it is required to design the layout pattern of the timing-considered cells according to timing constraints of the timing-considered cells. Therefore, in cases where the layout pattern of the timing-considered cells in the semiconductor integrated circuit is designed according to a conventional automatic cell placement and routing method (or called a place and route method) based on a timing driven layout technique, the timing constraints of the timing-considered cells are added to an automatic placement and routing tool, and a layout pattern of the timing-considered cells is designed so as to satisfy the timing constraints of the timing-considered cells.
However, in cases where a timing-free cell (for example, an asynchronous circuit), in which an input timing of a signal is not considered, is connected with the timing-considered cells on the signal path, it is impossible to design a layout pattern of the timing-considered cells and the timing-free cell according to the conventional automatic cell placement and routing method based on the timing driven layout technique while satisfying the timing constraints of the timing-considered cells.
FIG. 12 shows a plurality of cells placed on a signal path in a semiconductor integrated circuit. In FIG. 12, 21 indicates a timing-considered cell denoting a storing element such as a flip-flop or a latch. 22 indicates a timing-free cell in which an input timing of a signal is not considered. 23 indicates another timing-considered cell such as a combinational circuit. A signal passes through the cells 21, 22 and 23 placed on a signal path from the left side to the right side in FIG. 12. That is, a signal passing through the signal path is input to the first timing-considered cell 21 placed on the most left side, the first timing-considered cell 23, the timing-free cell 22, the second timing-considered cell 23 and the second timing-considered cell 21 placed on the most right side in that order. Each pair of cells adjacent to each other is connected with each other through a net. Each timing-considered cell has timing information indicating a timing constraint for a signal which is input to the timing-considered cell through a net. For example, a signal transmission delay time allowed for each timing-considered cell is considered within an allowable time range. Information of the set of the cells 21, 22 and 23 and a connection relationship among the cells 21, 22 and 23 connected with each other through nets are stored in a data base as a logical net list.
In the example of the cells 21, 22 and 23 shown in FIG. 12, because a net 24 connects the first timing-considered cell 21 and a signal input terminal (not shown) and because a net 25 connects the second timing-considered cells 21 and 23, it is required to design a layout pattern of cells 21, 22 and 23 placed on the signal path extending from the net 24 to the net 25 according to the conventional automatic cell placement and routing method based on the timing driven layout technique while using the logical net list and the timing information of the timing-considered cells and nets.
However, because no timing information of the timing-free cell 22 is prepared, a layout pattern of cells 21, 22 and 23 placed on the signal path from the net 24 to the net 25 cannot be designed according to the conventional automatic cell placement and routing method based on the timing driven layout technique. Therefore, it is required to manually check a signal transmission time period for each pair of timing-considered cells adjacent to each other.
As is described above, in cases where the timing-free cell having no timing information is placed on a signal path on which a plurality of timing-considered cells are placed, it becomes impossible to design a layout pattern of the timing-considered cells and the timing-free cell on the signal path according to the conventional automatic cell placement and routing method based on the timing driven layout technique, and it is required to manually design a layout pattern of the cells placed on the signal path while checking a transmission delay time of a signal for each timing-considered cell. Therefore, a design time required for the design of the layout pattern of the cells to be arranged in the semiconductor integrated circuit is lengthened, and there is a problem that a design efficiency for the design of the layout pattern of the cells is lowered.
An object of the present invention is to provide, with due consideration to the drawbacks of the conventional automatic cell placement and routing method, an automatic cell placement and routing method in which timing-considered cells to be arranged in a semiconductor integrated circuit is automatically placed at high speed in the design of a layout pattern of the timing-considered cells according to timing constraints of the timing-considered cells even though a timing-free cell is placed with the timing-considered cells on a signal path. Also, the object of the present invention is to provide a semiconductor integrated circuit in which timing-considered cells automatically placed according to the automatic cell placement and routing method in a layout pattern design are arranged with a timing-free cell.
The object is achieved by the provision of an automatic cell placement and routing method, comprising the steps of:
preparing a logical net list of a timing-free cell, a plurality of timing-considered cells and nets, through which the timing-free cell and the timing-considered cells are connected with each other, to be arranged in a semiconductor integrated circuit;
preparing dummy pin information to specify the timing-free cell written in the logical net list and to isolate the timing-free cell from the timing-considered cells and the nets by placing dummy pins on both sides of the timing-free cell;
preparing timing information indicating timing constraints of the timing-considered cells and the nets through which the timing-considered cells are connected a with each other; and
performing an automatic layout routing for the timing-considered cells according to the logical net list, the dummy pin information and the timing information to design a layout pattern of the timing-considered cells to be arranged in the semiconductor integrated circuit.
Also, a semiconductor integrated circuit comprises:
the timing-considered cells in which an input timing of a signal is considered and which are placed on a signal path; and
the timing-free cell in which an input timing of a signal is not considered and which is placed on the signal path on which the timing-considered cells are placed, wherein the layout pattern of the timing-considered cells is designed according to the automatic cell placement and routing method.
In the above steps of the automatic cell placement and routing method and the configuration of the semiconductor integrated circuit, the timing-free cell is isolated from the timing-considered cells by placing the dummy pins on both sides of the timing-free cell. Therefore, the timing-considered cells to be arranged in the semiconductor integrated circuit can be automatically placed in the design of a layout pattern of the timing-considered cells.
Accordingly, even though the timing-free cell having no timing information is placed on the signal path with the timing-considered cells respectively having timing information, a design time required for the design of a layout pattern of the timing-considered cells to be arranged in the semiconductor integrated circuit can be shortened, and a design efficiency for the design of the layout pattern of the timing-considered cells can be improved.
The object is also achieved by the provision of an automatic cell placement and routing method, comprising the steps of:
preparing a logical net list of a timing-free cell, a plurality of timing-considered cells and nets, through which the timing-free cell and the timing-considered cells are connected with each other, to be arranged in a semiconductor integrated circuit;
preparing dummy pin information to specify the timing-free cell written in the logical net list;
establishing the correspondence of the dummy pin information to the logical net list to place a dummy pin at a boundary between the timing-free cell and each timing-considered cell adjacent to the timing-free cell;
preparing timing information indicating timing constraints of the timing-considered cells and the nets through which the timing-considered cells are connected with each other;
establishing the correspondence of the timing information to the logical net list to allocate the timing information to the timing-considered cells written in the logical net list;
preparing dummy pin layout-position information indicating positions of the dummy pins in a layout pattern of the timing-considered cells;
performing a floor plan for the timing-considered cells according to the logical net list, the timing information and the dummy pin layout-position information; and
performing an automatic layout routing for a result of the floor plan to design a layout pattern of the timing-considered cells in the semiconductor integrated circuit.
Also, a semiconductor integrated circuit comprises:
the timing-considered cells in which an input timing of a signal is considered and which are placed on a signal path; and
the timing-free cell in which an input timing of a signal is not considered and which is placed on the signal path on which the timing-considered cells are placed, wherein the layout pattern of the timing-considered cells is designed according to the automatic cell placement and routing method.
In the above steps of the automatic cell placement and routing method and the configuration of the semiconductor integrated circuit, the timing-free cell is isolated from the timing-considered cells by placing the dummy pins at the boundaries between the timing-free cell and the group of timing-considered cells, and positions of the dummy pins in the layout pattern of the timing-considered cells are indicated by the dummy pin layout-position information. Therefore, the timing-considered cells to be arranged in the semiconductor integrated circuit can be automatically placed in the design of a layout pattern of the timing-considered cells.
Accordingly, even though the timing-free cell having no timing information is placed on the signal path with the timing-considered cells respectively having timing information, a design time required for the design of a layout pattern of the timing-considered cells to be arranged in the semiconductor integrated circuit can be shortened, and a design efficiency for the design of the layout pattern of the timing-considered cells can be improved.
The object is also achieved by the provision of an automatic cell placement and routing method, comprising the steps of:
preparing a logical net list of a timing-free cell, a plurality of timing-considered cells and nets, through which the timing-free cell and the timing-considered cells are connected with each other, to be arranged in a semiconductor integrated circuit;
preparing cell information of the timing-free cell for which the design of a layout pattern is not desired;
establishing the correspondence of the cell information to the logical net list to place a dummy pin at a boundary between the timing-free cell and each timing-considered cell adjacent to the timing-free cell;
preparing timing information indicating timing constraints of the timing-considered cells and the nets through which the timing-considered cells are connected with each other;
establishing the correspondence of the timing information to the logical net list to allocate the timing information to the timing-considered cells written in the logical net list;
preparing dummy pin layout-position information indicating positions of the dummy pins in a layout pattern of the timing-considered cells;
performing a floor plan for the timing-considered cells according to the logical net list, the timing information and the dummy pin layout-position information; and
performing an automatic layout routing for a result of the floor plan to design a layout pattern of the timing-considered cells in the semiconductor integrated circuit.
Also, a semiconductor integrated circuit comprises:
the timing-considered cells in which an input timing of a signal is considered and which are placed on a signal path; and
the timing-free cell in which an input timing of a signal is not considered and which is placed on the signal path on which the timing-considered cells are placed, wherein the layout pattern of the timing-considered cells is designed according to the automatic cell placement and routing method.
In the above steps of the automatic cell placement and routing method and the configuration of the semiconductor integrated circuit, the timing-free cell is specified by the cell information input by a user and is isolated from the timing-considered cells by placing the dummy pins at the boundaries between the timing-free cell and the group of timing-considered cells, and positions of the dummy pins in the layout pattern of the timing-considered cells are indicated by the dummy pin layout-position information. Therefore, the timing-considered cells to be arranged in the semiconductor integrated circuit can be automatically placed in the design of a layout pattern of the timing-considered cells.
Accordingly, even though the timing-free cell having no timing information is placed on the signal path with the timing-considered cells respectively having timing information, a design time required for the design of a layout pattern of the timing-considered cells to be arranged in the semiconductor integrated circuit can be shortened, and a design efficiency for the design of the layout pattern of the timing-considered cells can be improved.
The object is also achieved by the provision of an automatic cell placement and routing method, comprising the steps of:
preparing a logical net list of cells and nets, through which the cells are connected with each other, to be arranged in a semiconductor integrated circuit;
searching a cell library for cell information of each cell written in the logical net list;
automatically setting a specific cell, of which the cell information is not registered in the cell library or of which the cell information is insufficient in the cell library, as a timing-free cell for which the design of a layout pattern is not desired, the cells of the logical net list other than the specific cell being called timing-considered cells;
establishing the correspondence of a dummy pin to the logical net list to place the dummy pin at a boundary between the timing-free cell and each timing-considered cell adjacent to the timing-free cell;
preparing timing information indicating timing constraints of the timing-considered cells and the nets through which the timing-considered cells are connected with each other;
establishing the correspondence of the timing information to the logical net list to allocate the timing information to the timing-considered cells written in the logical net list;
preparing dummy pin layout-position information indicating positions of the dummy pins in a layout pattern of the timing-considered cells;
performing a floor plan for the timing-considered cells according to the logical net list, the timing information and the dummy pin layout-position information; and
performing an automatic layout routing for a result of the floor plan to design a layout pattern of the timing-considered cells in the semiconductor integrated circuit.
Also, a semiconductor integrated circuit comprises:
the timing-considered cells in which an input timing of a signal is considered and which are placed on a signal path; and
the timing-free cell in which an input timing of a signal is not considered and which is placed on the signal path on which the timing-considered cells are placed, wherein the layout pattern of the timing-considered cells is designed according to the automatic cell placement and routing method.
In the above steps of the automatic cell placement and routing method and the configuration of the semiconductor integrated circuit, the timing-free cell having no timing information is automatically specified by searching a cell library for cell information of each cell written in a logical net list, the timing-free cell is isolated from the timing-considered cells by placing the dummy pins at the boundaries between the timing-free cell and the group of timing-considered cells, and positions of the dummy pins in the layout pattern of the timing-considered cells are indicated by the dummy pin layout-position information. Therefore, the timing-considered cells to be arranged in the semiconductor integrated circuit can be automatically placed in the design of a layout pattern of the timing-considered cells.
Accordingly, even though the timing-free cell having no timing information is placed on the signal path with the timing-considered cells respectively having timing information, a design time required-for the design of a layout pattern of the timing-considered cells to be arranged in the semiconductor integrated circuit can be shortened, and a design efficiency for the design of the layout pattern of the timing-considered cells can be improved.
It is preferred that the step of establishing the correspondence of a dummy pin to the logical net list comprises the steps of:
placing end point information indicating an end point of a timing check at the boundary as the dummy pin in cases where the boundary is placed on an input pin side of the timing-free cell or in cases where a timing-considered cell, which drives a net connected with an input pin of the timing-free cell, is written in the logical net list; and
placing start point information indicating a start point of a timing check at the boundary as the dummy pin in cases where the boundary is placed on an output pin side of the timing-free cell or in cases where a timing-considered cell, which drives a net connected with an output pin of the timing-free cell, is written in the logical net list.
In the above steps, a layout area of the timing-considered cells, for which a timing check is required, can be reliably determined according to the start point information and the end point information.
It is also preferred that the step of preparing dummy pin layout-position information includes:
indicating an absolute position of each dummy pin in the layout pattern as a first case, relative positions of the dummy pins in the layout pattern as a second case, absolute positions of a part of dummy pins or relative positions of a part of dummy pins as a third case or the combination of the first, second and third cases as a fourth case according to the dummy pin layout-position information, the step of performing a floor plan comprises the steps of:
placing the dummy pins in the layout pattern of the timing-considered cells according to the dummy pin layout-position information;
determining a layout area of the timing-considered cells; and
performing the floor plan according to the timing information.
In the above steps, absolute positions of the dummy pins in the layout pattern, relative positions of the dummy pins in the layout pattern, absolute positions of a part of dummy pins or relative positions of a part of dummy pins or the combination of the above are indicated according to the dummy pin layout-position information. Therefore, the positions of the dummy pins can be reliably indicated.
It is also preferred that the step of preparing dummy pin layout-position information comprises the steps of:
allocating a name to each dummy pin; and
distinguishing the timing-free cell and a group of the timing-considered cells from each other according to the names.
In the above steps, the dummy pins can be distinguished from each other according to the names allocated to the dummy pins. Therefore, a layout area of the timing-considered cells can be reliably determined.
It is also preferred that the step of preparing dummy pin layout-position information further comprises the steps of;
determining the whole area of the timing-free cell and the timing-considered cells to be arranged in the semiconductor integrated circuit;
determining a position of the timing-free cell and a position of the group of timing-considered cells in the semiconductor integrated circuit according to a size of the timing-free cell and a size of the group of timing-considered cells; and
placing the dummy pins at the boundaries between the timing-free cell and the group of timing-considered cells.
In the above steps, the position of the timing-free cell and the position of the group of timing-considered cells in the semiconductor integrated circuit are determined according to a size of the timing-free cell and a size of the group of timing-considered cells. Therefore, the timing-free cell and the group of timing-considered cells can be appropriately arranged in the semiconductor integrated circuit.
It is also preferred that the step of performing an automatic layout routing comprises the steps of:
placing each of the cells written in the logical net list;
determining positions of the dummy pins in the layout pattern of the cells according to relative positions of the cells;
placing the dummy pins at the determined positions;
performing a rough routing for the timing-considered cells according to the placement of the dummy pins; and
performing a detailed routing for the timing-considered cells.
In the above steps, after the dummy pins are placed at the determined positions, a layout pattern of the timing-considered cells is designed in the rough routing and the detailed routing. Therefore, the layout pattern of the timing-considered cells can be reliably designed.
It is also preferred that the step of performing an automatic layout routing comprises the steps of:
placing each of the cells written in the logical net list;
performing a rough routing for the timing-considered cells;
determining positions of the dummy pins in the layout pattern of the cells according to relative positions of the cells;
placing the dummy pins at the determined positions; and
performing a detailed routing for the timing-considered cells according to the placement of the dummy pins.
In the above steps, after the rough routing is performed, the dummy pins are placed at the determined positions, and a layout pattern of the timing-considered cells is designed in the detailed routing. Therefore, the layout pattern of the timing-considered cells can be reliably designed.
It is also preferred that the step of performing an automatic layout routing comprises the steps of:
placing each of the cells written in the logical net list;
performing a rough routing for the timing-considered cells;
performing a detailed routing for the timing-considered cells;
determining positions of the dummy pins in the layout pattern of the cells according to relative positions of the cells; and
placing the dummy pins at the determined positions.
In the above steps, after the rough routing and the detailed routing are performed, the dummy pins are placed at the determined positions. Therefore, the layout pattern of the timing-considered cells can be reliably designed.
It is also preferred that the step of performing an automatic layout routing comprises the steps of:
placing each of the cells written in the logical net list;
determining positions of the dummy pins in the layout pattern of the cells according to relative positions of the cells;
placing the dummy pins at the determined positions;
performing a rough routing for the timing-considered cells according to the placement of the dummy pins;
determining optimized positions of the dummy pins;
changing the placement of the dummy pins to the optimized positions; and
performing a detailed routing for the timing-considered cells.
In the above steps, after the rough is performed, the dummy pins are rearranged at the optimized positions, and the detailed routing is performed. Therefore, the layout pattern of the timing-considered cells can be reliably designed.